1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit having a plurality of power domains.
2. Description of the Related Art
The operating power supply voltage of a semiconductor integrated circuit such as a system large-scale integrated circuit (LSI) tends to lower owing to downsizing of elements such as transistors caused by micropatterning in the semiconductor process.
Also, to reduce the power consumption of a semiconductor integrated circuit, a plurality of circuit blocks forming the semiconductor integrated circuit are operated by different power supply voltages in accordance with the functions of the circuit blocks. A clustered voltage scaling (CVS) method and voltage-island method are known as methods of forming a plurality of circuit blocks in accordance with different power supply voltages.
To prevent a crowbar current between circuit blocks, however, these methods impose limitations on the connections of the circuit blocks or require latch circuits, flip-flops, level converters, or the like as interface circuits for signals flowing between the circuit blocks. Also, the latch circuits, flip-flops, level converters, or the like inserted between the circuit blocks must be designed so as not to generate any crowbar current at an assumed power supply voltage. A design like this imposes limitations on the configuration of the circuit blocks.
In addition, the overhead of the interface circuits inserted between the circuit blocks makes it difficult to divide the circuit blocks by decreasing the granularity. Furthermore, when inserting flip-flops between the circuit blocks, an appropriate clock signal must be supplied to these flip-flops. Although this clock signal can be the same as a clock signal for other circuits, one pipe-line stage must be added in this case. This increases the area of the semiconductor integrated circuit.
As a related technique of this type, a semiconductor integrated circuit capable of suppressing a crowbar current in an interface circuit is disclosed (Jpn. Pat. Appln. KOKAI Publication No. 2004-165993).